Abstracted Instruction Cache of TITAC2 — As a Benchmark Circuit for Timed Asynchronous Circuit Verification
نویسنده
چکیده
As a benchmark circuit for timed asynchronous circuit verification, we have developed an abstracted version of TITAC 2 instruction cache sub-system and its formal specification. This document shows all the figures of the gate level sub-circuits which compose the abstracted instruction cache. A time Petri net model for the formal specification is also shown with the detailed explanation. The text files describing those circuits and Petri nets can be obtained from http://yoneda–www.cs.titech.ac.jp/∼yoneda/pub.html.
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تاریخ انتشار 1999